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Features
* Single Voltage Operation * * * * * * * * *
- 5V Read - 5V Reprogramming Fast Read Access Time - 55 ns Internal Program Control and Timer 8K Word Boot Block With Lockout Fast Erase Cycle Time - 10 seconds Word-By-Word Programming - 10 s/Word Typical Hardware Data Protection DATA Polling For End Of Program Detection Small 10 x 14 VSOP Package Typical 10,000 Write Cycles
Description
The AT49F516 is a 5-volt only in-system programmable and erasable Flash Memory. It's 512K of memory is organized as 32,768 words by 16 bits. Manufactured with Atmel's advanced nonvolatile CMOS technology, the devices offer access times to 55 ns with power dissipation of just 275 mW over the commercial temperature range. When the device is deselected, the CMOS standby current is less than 100 A.
512K (32K x 16) 5-volt Only Flash Memory AT49F516 Preliminary
(continued)
Pin Configurations
Pin Name A0 - A14 CE OE WE I/O0 - I/O15 NC Function Addresses Chip Enable Output Enable Write Enable Data Inputs/Outputs No Connect
A0 A1 A2 A3 A4 A5 A6 A7 A8 GND A9 A10 A11 A12 A13 A14 NC NC WE VCC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
VSOP Top View Type 1 10 x 14 mm
10 x 14 mm
PLCC Top View
I/O13 I/O14 I/O15 CE NC NC VCC WE NC NC A14
I/O3 I/O2 I/O1 I/O0 OE DC A0 A1 A2 A3 A4
18 19 20 21 22 23 24 25 26 27 28
I/O12 I/O11 I/O10 I/O9 I/O8 GND NC I/O7 I/O6 I/O5 I/O4
7 8 9 10 11 12 13 14 15 16 17
39 38 37 36 35 34 33 32 31 30 29
A13 A12 A11 A10 A9 GND NC A8 A7 A6 A5
40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21
OE I/O0 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/07 GND I/O8 I/O9 I/O10 I/O11 I/O12 I/O13 I/O14 I/O15 NC CE
6 5 4 3 2 1 44 43 42 41 40
Rev. 1089B-10/98
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To allow for simple in-system reprogrammability, the AT49F516 does not require high input voltages for programming. Five-volt-only commands determine the read and programming operation of the device. Reading data out of the device is similar to reading from an EPROM. Reprogramming the AT49F516 is performed by erasing a block of data (entire chip or main memory block) and then programming on a word by word basis. The typical word programming time is a fast 10 s. The end of a program cycle can be optionally detected by the DATA polling fea-
ture. Once the end of a byte program cycle has been detected, a new access for a read or program can begin. The typical number of program and erase cycles is in excess of 10,000 cycles. The optional 8K words boot block section includes a reprogramming write lock out feature to provide data integrity. The boot sector is designed to contain user secure code, and when the feature is enabled, the boot sector is permanently protected from being erased or reprogrammed.
Block Diagram
VCC GND OE WE CE DATA INPUTS/OUTPUTS I/O15 - I/O0 16 OE, CE, AND WE LOGIC DATA LATCH INPUT/OUTPUT BUFFERS Y-GATING 7FFFH X DECODER MAIN MEMORY (24K WORDS) OPTIONAL BOOT BLOCK (8K WORDS) 0000H 2000H 1FFFH
Y DECODER ADDRESS INPUTS
Device Operation
READ: The AT49F516 is accessed like an EPROM. When CE and OE are low and WE is high, the data stored at the memory location determined by the address pins is asserted on the outputs. The outputs are put in the high impedance state whenever CE or OE is high. This dual-line control gives designers flexibility in preventing bus contention. CHIP ERASE: When the boot block programming lockout feature is not enabled, the boot block and the main memory block will erase together from the same chip erase command (See command definitions table). If the boot block lockout function has been enabled, data in the boot section will not be erased. However, data in the main memory section will be erased. After a chip erase, the device will return to the read mode. MAIN MEMORY ERASE: As an alternative to the chip erase, a main memory block erase can be performed which will erase all bytes not located in the boot block region to an FFH. Data located in the boot region will not be changed during a main memory block erase. The Main Memory Erase command is a six bus cycle operation. The address (5555H) is latched on the falling edge of the sixth cycle while the 30H data input is latched on the rising edge of WE. The main memory erase starts after the rising edge of WE of the sixth cycle. Please see Main Memory Erase cycle waveforms. The Main Memory Erase operation is internally controlled; it will automatically time to completion. WORD PROGRAMMING: Once the memory array is erased, the device is programmed (to a logical "0") on a word-by-word basis. Please note that a data "0" cannot be programmed back to a "1"; only erase operations can convert "0"s to "1"s. Programming is accomplished via the internal device command register and is a 4 bus cycle operation (please refer to the Command Definitions table). The device will automatically generate the required internal program pulses. The program cycle has addresses latched on the falling edge of WE or CE, whichever occurs last, and the data latched on the rising edge of WE or CE, whichever occurs first. Programming is completed after the specified tBP cycle time. The DATA polling feature may also be used to indicate the end of a program cycle. BOOT BLOCK PROGRAMMING LOCKOUT: The device has one designated block that has a programming lockout feature. This feature prevents programming of data in the designated block once the feature has been enabled. The size of the block is 8K words. This block, referred to as the boot block, can contain secure code that is used to bring up the system. Enabling the lockout feature will allow the boot code to stay in the device while data in the rest of the
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AT49F516
AT49F516
device is updated. This feature does not have to be activated; the boot block's usage as a write protected region is optional to the user. The address range of the boot block is 0000H to 1FFFH. Once the feature is enabled, the data in the boot block can no longer be erased or programmed. Data in the main memory block can still be changed through the regular programming method and can be erased using either the chip erase or the main memory block erase command. To activate the lockout feature, a series of six program commands to specific addresses with specific data must be performed. Please refer to the Command Definitions table. BOOT BLOCK LOCKOUT DETECTION: A software method is available to determine if programming of the boot block section is locked out. When the device is in the software product identification mode (see Software Product Identification Entry and Exit sections) a read from address location 0002H will show if programming the boot block is locked out. If the data on I/O0 is low, the boot block can be programmed; if the data on I/O0 is high, the program lockout feature has been activated and the block cannot be programmed. The software product identification exit code should be used to return to standard operation. PRODUCT IDENTIFICATION: The product identification mode identifies the device and manufacturer as Atmel. It may be accessed by hardware or software operation. The hardware operation mode can be used by an external programmer to identify the correct programming algorithm for the Atmel product. For details, see Operating Modes (for hardware operation) or Software Product Identification. The manufacturer and device code is the same for both modes. DATA POLLING: The AT49F516 features DATA polling to indicate the end of a program or erase cycle. During a program cycle an attempted read of the last byte loaded will result in the complement of the loaded data on I/O7. Once the program cycle has been completed, true data is valid on all outputs and the next cycle may begin. DATA polling may begin at any time during the program cycle. TOGGLE BIT: In addition to DATA polling the AT49F516 provides another method for determining the end of a program or erase cycle. During a program or erase operation, successive attempts to read data from the device will result in I/O6 toggling between one and zero. Once the program cycle has completed, I/O6 will stop toggling and valid data will be read. Examining the toggle bit may begin at any time during a program cycle. HARDWARE DATA PROTECTION: Hardware features protect against inadvertent programs to the AT49F516 in the following ways: (a) VCC sense: if VCC is below 3.8V (typical), the program function is inhibited. (b) Program inhibit: holding any one of OE low, CE high or WE high inhibits program cycles. (c) Noise filter: Pulses of less than 15 ns (typical) on the WE or CE inputs will not initiate a program cycle.
3
Command Definition (in Hex)(1)
Command Sequence Read Chip Erase Main Memory Erase Word Program Boot Block Lockout(2) Product ID Entry Product ID Exit Product ID Exit Notes:
(3) (3)
Bus Cycles 1 6 6 4 6 3 3 1
1st Bus Cycle Addr Addr 5555 5555 5555 5555 5555 5555 xxxx Data DOUT AA AA AA AA AA AA F0
2nd Bus Cycle Addr Data
3rd Bus Cycle Addr Data
4th Bus Cycle Addr Data
5th Bus Cycle Addr Data
6th Bus Cycle Addr Data
2AAA 2AAA 2AAA 2AAA 2AAA 2AAA
55 55 55 55 55 55
5555 5555 5555 5555 5555 5555
80 80 A0 80 90 F0
5555 5555 Addr 5555
AA AA DIN AA
2AAA 2AAA
55 55
5555 5555
10 30
2AAA
55
5555
40
1. The DATA FORMAT in each bus cycle is as follows: I/O15 - I/O8 (Don't Care); I/O7 - I/O0 (Hex). 2. The 8K word boot sector has the address range 00000H to 1FFFH. 3. Either one of the Product ID Exit commands can be used.
Absolute Maximum Ratings*
Temperature Under Bias ................................ -55C to +125C Storage Temperature ..................................... -65C to +150C All Input Voltages (including NC Pins) with Respect to Ground ...................................-0.6V to +6.25V All Output Voltages with Respect to Ground .............................-0.6V to VCC + 0.6V Voltage on OE with Respect to Ground ...................................-0.6V to +13.5V *NOTICE: Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
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AT49F516
AT49F516
DC and AC Operating Range
AT49F516-55 Operating Temperature (Case) VCC Power Supply Com. Ind. 0C - 70C -40C - 85C 5V 10% AT49F516-70 0C - 70C -40C - 85C 5V 10% AT49F516-90 0C - 70C -40C - 85C 5V 10%
Operating Modes
Mode Read Program
(2)
CE VIL VIL VIH X X X
OE VIL VIH X
(1)
WE VIH VIL X VIH X X
Ai Ai Ai X
I/O DOUT DIN High Z
Standby/Write Inhibit Program Inhibit Program Inhibit Output Disable Product Identification Hardware
X VIL VIH
High Z
VIL
VIL
VIH
A1 - A14 = VIL, A9 = VH,(3), A0 = VIL A1 - A14 = VIL, A9 = VH,(3), A0 = VIH A0 = VIL, A1 - A14 = VIL A0 = VIH, A1 - A14 = VIL
Manufacturer Code(4) Device Code(4) Manufacturer Code(4) Device Code(4)
Software(5) Notes: 1. X can be VIL or VIH. 2. Refer to AC Programming Waveforms. 3. VH = 12.0V 0.5V. 4. Manufacturer Code: 1FH, Device Code: 100001XX (binary). 5. See details under Software Product Identification Entry/Exit.
DC Characteristics
Symbol ILI ILO ISB1 ISB2 ICC (1) VIL VIH VOL VOH1 VOH2 Note: Parameter Input Load Current Output Leakage Current VCC Standby Current CMOS VCC Standby Current TTL VCC Active Current Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage Output High Voltage CMOS 1. In the erase mode, ICC is 90 mA. IOL = 2.1 mA IOH = -400 A IOH = -100 A; VCC = 4.5V 2.4 4.2 2.0 0.45 Condition VIN = 0V to VCC VI/O = 0V to VCC Com. CE = VCC - 0.3V to VCC CE = 2.0V to VCC f = 5 MHz; IOUT = 0 mA Ind. Min Max 10 10 100 300 3 50 0.8 Units A A A A mA mA V V V V V
5
AC Read Characteristics
AT49F516-55 Symbol tACC tCE
(1)
AT49F516-70 Min Max 70 70 35 0 0 25
AT49F516-90 Min Max 90 90 0 0 0 40 25 Units ns ns ns ns ns
Parameter Address to Output Delay CE to Output Delay OE to Output Delay CE or OE to Output Float Output Hold from OE, CE or Address, whichever occurred first
Min
Max 55 55 30
tOE(2) tDF(3)(4) tOH
0 0
25
AC Read Waveforms(1)(2)(3)(4)
Notes:
1. 2. 3. 4.
CE may be delayed up to tACC - tCE after the address transition without impact on tACC. OE may be delayed up to tCE - tOE after the falling edge of CE without impact on tCE or by tACC - tOE after an address change without impact on tACC. tDF is specified from OE or CE whichever occurs first (CL = 5 pF). This parameter is characterized and is not 100% tested.
Input Test Waveforms and Measurement Level
Output Test Load
55/70 ns
5.0V 1.8K OUTPUT PIN 1.8K OUTPUT PIN 1.3K 100 pF
90 ns
5.0V
tR, tF < 5 ns
1.3K
30 pF
Pin Capacitance
f = 1 MHz, T = 25C(1)
Symbol CIN COUT Note: Typ 4 8 Max 6 12 Units pF pF Conditions VIN = 0V VOUT = 0V
1. This parameter is characterized and is not 100% tested.
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AT49F516
AT49F516
AC Word Load Characteristics
Symbol tAS, tOES tAH tCS tCH tWP tDS tDH, tOEH tWPH Parameter Address, OE Set-up Time Address Hold Time Chip Select Set-up Time Chip Select Hold Time Write Pulse Width (WE or CE) Data Set-up Time Data, OE Hold Time Write Pulse Width High Min 0 50 0 0 90 50 0 90 Max Units ns ns ns ns ns ns ns ns
AC Word Load Waveforms
WE Controlled
OE tOES ADDRESS CE tAS tCS tWPH tWP tDS DATA IN tDH tAH tCH tOEH
WE
CE Controlled
OE tOES ADDRESS tAS WE tCS CE tWPH tWP tDS DATA IN tDH tAH tCH tOEH
7
Program Cycle Characteristics
Symbol tBP tAS tAH tDS tDH tWP tWPH tEC Parameter Word Programming Time Address Set-up Time Address Hold Time Data Set-up Time Data Hold Time Write Pulse Width Write Pulse Width High Erase Cycle Time 0 50 50 0 90 90 10 Min Typ 10 Max 50 Units s ns ns ns ns ns ns seconds
Program Cycle Waveforms
A0-A14
Main Memory or Chip Erase Cycle Waveforms
OE
CE
tWP tWPH
WE
tAS tAH
5555
tDH
2AAA 5555 5555 2AAA 5555
A0-A14
tDS
tEC
55 WORD 1 80 WORD 2 AA WORD 3 55 WORD 4 NOTE 2 WORD 5
DATA
AA WORD 0
Notes:
1. 2.
OE must be high only when WE and CE are both low. For chip erase, the address should be 10H. For a main memory erase the data should be 30H.
8
AT49F516
AT49F516
Data Polling Characteristics(1)
Symbol tDH tOEH tOE tWR Notes: Parameter Data Hold Time OE Hold Time OE to Output Delay
(2)
Min 10 10
Typ
Max
Units ns ns ns
Write Recovery Time 1. These parameters are characterized and not 100% tested. 2. See tOE spec in AC Read Characteristics.
0
ns
Data Polling Waveforms
A0-A14
Toggle Bit Characteristics(1)
Symbol tDH tOEH tOE tOEHP tWR Notes: Parameter Data Hold Time OE Hold Time OE to Output Delay(2) OE High Pulse Write Recovery Time 1. These parameters are characterized and not 100% tested. 2. See tOE spec in AC Read Characteristics. 150 0 Min 10 10 Typ Max Units ns ns ns ns ns
Toggle Bit Waveforms(1)(2)(3)
Notes:
1. 2. 3.
Toggling either OE or CE or both OE and CE will operate toggle bit. The tOEHP specification must be met by the toggling input(s). Beginning and ending state of I/O6 will vary. Any address location may be used but the address should not vary.
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Software Product Identification Entry(1)
LOAD DATA AA TO ADDRESS 5555
Boot Block Lockout Enable Algorithm(1)
LOAD DATA AA TO ADDRESS 5555
LOAD DATA 55 TO ADDRESS 2AAA
LOAD DATA 55 TO ADDRESS 2AAA
LOAD DATA 90 TO ADDRESS 5555
LOAD DATA 80 TO ADDRESS 5555
ENTER PRODUCT IDENTIFICATION MODE(2)(3)(5)
LOAD DATA AA TO ADDRESS 5555
Software Product Identification Exit(1)
LOAD DATA AA TO ADDRESS 5555 OR LOAD DATA F0 TO ANY ADDRESS
LOAD DATA 55 TO ADDRESS 2AAA
LOAD DATA 40 TO ADDRESS 5555
LOAD DATA 55 TO ADDRESS 2AAA
EXIT PRODUCT IDENTIFICATION MODE(4)
PAUSE 1 second(2)
LOAD DATA F0 TO ADDRESS 5555
Notes:
1. 2.
Data Format: I/O15 - I/O8 (Don't Care); I/O7 - I/O0 (Hex); Address Format: A14 - A0 (Hex). Boot block lockout feature enabled.
EXIT PRODUCT IDENTIFICATION MODE(4)
Notes:
1. 2.
Data Format: I/O15 - I/O8 (Don't Care); I/O7 - I/O0 (Hex); Address Format: A14 - A0 (Hex). A1 - A14 = VIL. Manufacture Code is read for A0 = VIL; Device Code is read for A0 = VIH. The device does not remain in identification mode if powered down. The device returns to standard operation mode. Manufacturer Code: 1FH Device Code: 100001XX (binary)
3. 4. 5.
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AT49F516
AT49F516
Ordering Information(1)
tACC (ns) 55 ICC (mA) Active 50 50 70 50 50 90 50 50 Note: Standby 0.1 0.3 0.1 0.3 0.1 0.3 Ordering Code AT49F516-55JC AT49F516-55VC AT49F516-55JI AT49F516-55VI AT49F516-70JC AT49F516-70VC AT49F516-70JI AT49F516-70VI AT49F516-90JC AT49F516-90VC AT49F516-90JI AT49F516-90VI Package 44J 40V 44J 40V 44J 40V 44J 40V 44J 40V 44J 40V Operation Range Commercial (0 to 70C) Industrial (-40 to 85C) Commercial (0 to 70C) Industrial (-40 to 85C) Commercial (0 to 70C) Industrial (-40 to 85C)
1. The AT49F516 has as optional boot block feature. The part number shown in the Ordering Information table is for devices with the boot block in the lower address range (i.e., 0000H to 1FFFH). Users requiring the boot block to be in the higher address range should contact Atmel.
Package Type 44J 40V 44-Lead, Plastic, J-Leaded Chip Carrier Package (PLCC) 40-Lead, Thin Small Outline Package (VSOP) (10 mm x 14 mm)
11
Packaging Information
44J, 44-Lead, Plastic J-Leaded Chip Carrier (PLCC) Dimensions in Inches and (Millimeters)
JEDEC STANDARD MS-018 AC
40V, 40-Lead, Plastic Thin Small Outline Package (TSOP) Dimensions in Millimeters and (Inches)*
.045(1.14) X 45
PIN NO. 1 IDENTIFY
.045(1.14) X 30 - 45
.012(.305) .008(.203)
.656(16.7) SQ .650(16.5) .032(.813) .026(.660) .695(17.7) SQ .685(17.4)
.630(16.0) .590(15.0) .021(.533) .013(.330)
.050(1.27) TYP .500(12.7) REF SQ
.043(1.09) .020(.508) .120(3.05) .090(2.29) .180(4.57) .165(4.19)
.022(.559) X 45 MAX (3X)
*Controlling dimension: millimeters
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AT49F516
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Fax-on-Demand
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e-mail
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Web Site
http://www.atmel.com
BBS
1-(408) 436-4309
(c) Atmel Corporation 1998. Atmel Cor poration makes no warranty for the use of its products, other than those expressly contained in the Company's standard warranty which is detailed in Atmel's Terms and Conditions located on the Company's website. The Company assumes no responsibility for any errors which may appear in this document, reserves the right to change devices or specifications detailed herein at any time without notice, and does not make any commitment to update the information contained herein. No licenses to patents or other intellectual proper ty of Atmel are granted by the Company in connection with the sale of Atmel products, expressly or by implication. Atmel's products are not authorized for use as critical components in life suppor t devices or systems. Marks bearing
(R)
and/or
TM
are registered trademarks and trademarks of Atmel Corporation. Printed on recycled paper.
1089B-10/98/xM
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